Reconfigurable electro-optical logic gates using a 2-layer multilayer perceptron

In this work, we aim to use the optical amplifiers, directional couplers and phase modulators to build the electro-optical gates. Thanks to the 2-layer-multilayer-perceptron structure, the inversion of matrix is performed to obtain the coupling ratio of the directional couplers and the phase delay of the phase modulators. The electro-optical OR, AND, XOR, NAND, NOR and XNOR gates are demonstrated. Moreover, we not only study the results under the ideal condition of device, but also discuss the imperfect situation with 1% error of fabrication or operation to study the tolerance of this system. Through our simulation results, the visibility of the gate output can be higher than 0.83. The gates can be fabricated in a silicon-based chip to develop the integrated optics computing system.

www.nature.com/scientificreports/ is removed in this new design. The switching time between 0 and 1 for the output of the gates can be shortened. In this work, the matrix inversion is performed to calculate the coupling ratio of the DCs and the phase delay of the PMs using the target output of the logic gates in the same optical configuration. The reconfigurable electrooptical OR, AND, XOR, NAND, NOR and XNOR gates formed by one optical structure are demonstrated.

Design of the 2-layer-multilayer-perceptron structure
It is known that RC system has been extensively used in the development of logic gates, waveform recognition, and rainfall prediction 5,[22][23][24] . This system is composed of the input weight matrix W in , the recurrent weight matrix W , and the readout matrix W out . The input matrix W in is used to scale the size of the input data to the size of the matrix W. The value of the elements in W in and W is chosen randomly. In this study, the learning is completed in a single pass-through training data. The optimal readout matrix W out is used to generate the output of the RC system. In RC system, the neuron can be described as a function of the current input and its previous calculation result which can be expressed by 25 where the function f is the nonlinear activation function of the neuron. Usually, the hyperbolic tangent function, tanh(), is used as the nonlinear activation function to converge the output value of neuron within − 1 and 1 26 . In this research, the non-linear function of our optical neuron is provided by the optical amplifiers. (The optical setup is shown in Fig. 1.) L is the leaky rate which is a real number from 0 to 1. However, since we do not use the recurrent property of RC in the optical neural network, L and W are set to be 1 and null, respectively producing a 2-layer MLP structure. u(n) represents the n-th input data. Thus, the reservoir activation state, X(n) , is modified to f W in u(n) . The network target output Y target is given by In Eq. (3), M and N are the number of the neurons and the number of the input data, respectively. By collecting the training data X and the target training signals Y target , the readout matrix W out can be obtained by inversing the matrix X from Eq. (2).
The main feature of 2-layer MLP is the fact that the training (or the optimization) is done by dealing with the readout matrix W out using the inverse of the matrix X. As we mentioned above, once we obtain the elements of W out , we could deduce the coupling ratio and phase in our DCs and PMs, respectively. This will be detailed . . . X M (2) . . . www.nature.com/scientificreports/ in the next section. Through this method, we can obtain the parameters of the optical devices in this optical neural network. Figure 1 illustrates the optical setup of our EO neural-network-based logic gates. The CW laser source at the wavelength of 1550 nm with the power of 0.1 W is launched into the DC in of our logic gate. The optical nonlinear effect of the optical fibers which connect the optical devices are ignored. This DC in with the coupling ratio of 50% is used to divide equally the input light into two light beams. The two light beams are launched into the two phase modulators (PM A and PM B in Fig. 1) individually. The half-wave voltage V π of the PM A and PM B is set randomly to be 1 V and 2 V, respectively. The input signals A and B are applied on the phase modulators PM A and PM B , respectively. The applied voltages are 0 or 1 V of the phase modulators to present the logic 0 and 1, respectively. PM A and PM B are connected to the directional coupler DC A . After that, the output signals of DC A are launched into DC B and DC C . DC A , DC B and DC C serve as the input matrix W in of the 2-layer MLP in which the values of the elements are chosen randomly. The coupling ratio of DC A , DC B and DC C is therefore set randomly. In our research, for the example of the XOR gate, the coupling ratios of the DC A , DC B and DC C are set randomly to be 0.56, 0.83 and 0.96, respectively. The four outputs of the DC B and DC C are connected to the optical amplifiers A 1 , A 2 , A 3 and A 4 , individually. The optical gain of the amplifiers is given by G o /(1 + G 0 P/P sat ) where G 0 , P, P sat are the small signal power gain, the power of the input light, and the saturation output power, respectively. For all amplifiers, the small signal power gain and the saturation output power are set to be 30 dB and 30dBm, respectively. The optical amplifiers provide the non-linear function which is required for 2-layer MLP system. The complex electric field of the output light of the amplifiers A 1 , A 2 , A 3 and A 4 are denoted by X 1 , X 2 , X 3 and X 4 , respectively, which are regarded as the output of the neurons. Therefore, the number of the neurons, M in Eqs. (3) and (4) is 4. In other words, an optical amplifier can be regarded as an optical neuron. The readout matrix W out is composed of the 3 phase modulators PM 1 , PM 2 and PM 3 as well as the 3 directional couplers DC 1 , DC 2 and DC 3 . ∅ 1 , ∅ 2 and ∅ 3 are the phase delay of the phase modulators PM 1 , PM 2 and PM 3 , respectively. α 1 , α 2 and α 3 are the coupling ratios of the DC 1 , DC 2 and DC 3 , respectively. The general formula of the output of electric field for the phase modulator and the directional coupler can be given by Eqs. (6) and (7), respectively.

Methods
where X in and X out represent the complex input and output electric fields of the components, respectively. ∅ and α are the phase delay of the phase modulators and the coupling ratio of the 2 by 2 DCs, respectively. The two input lights in the directional coupler are interfered. Using Eqs. (6) and (7), the complex electric field of the output light of the whole system Y target can be derived by The first step of the design process is to define the gate. For example, for an XOR gate, the possible recombination of the input signals A and B are (0, 0), (0, 1 V), (1 V, 0) and (1 V, 1 V). Thus, in Eq. (4), the number of the possible recombination of the input signals, N , is 4. The corresponding result Y target for the XOR gate are [0 1 1 0]. The complex electric fields X 1 , X 2 , X 3 and X 4 are located at the output of A 1 , A 2 , A 3 and A 4 , respectively, as shown in Fig. 1. For each recombination of the input signals, the complex values of X 1 , X 2 , X 3 and X 4 are collected to form the 4 by 4 matrix X of Eq. (4). According to Eq. (5), the values of w 1 , w 2 , w 3 and w 4 of the 1 by 4 matrix W out can be obtained using Y target and X. The coefficients of the terms X 1 , X 2 , X 3 and X 4 in Eq. (8) are equal to the 4 complex values w 1 , w 2 , w 3 and w 4 of W out forming 4 simultaneous equations. The phases of the complex numbers w 1 , w 2 , w 3 and w 4 are denoted by θ 1 , θ 2 , θ 3 and θ 4 . The boundary conditions for α 1 , α 2 , α 3 , are real numbers between 0 and 1. By solving the simultaneous equations, α 1 , α 2 , α 3 , ∅ 1 , ∅ 2 and ∅ 3 can be obtained by

Results and discussion
The  Fig. 1, α A , α B and α C , are chosen randomly for 100 times to obtain the best tolerance. The detail calculation of tolerance will be discussed in the next section. The obtained α A , α B and α C for each gate are listed in Table 1. The corresponding coupling ratio of the directional couplers DC 1 , DC 2 , DC 3 and the phase delay of the phase modulators PM 1 , PM 2 , PM 3 calculated through Eqs. (2)- (14) are listed in Table 2. The output powers of the OR, AND, XOR, NAND, NOR and XNOR logic gates for different input signals A and B are shown in Fig. 2. For the electro-optical logic gates, the relation between the input signals and the output of the 2-layer MLP system follows the truth table of the corresponding logic gates. The reconfigurable logic gate can be achieved by tuning the parameters of the directional couplers [27][28][29][30] and phase modulators 31 as listed in Tables 1 and 2. It is worth mentioning that the phase delay of the phase modulators for NOR gate is close to null revealing that the phase modulators PM 1 , PM 2 and PM 3 might be removed. For the other gates, it is might be possible to find the solution to remove the phase modulators. We use the visibility of the output signals of logic 0 and logic 1 to evaluate the tolerance of our logic gates. The definition of visibility is shown in Eq. (15) 32 where I 1 min and I 0 max are the minimum light intensity of the high level (logic 1) and the maximum light intensity of the low level (logic 0), respectively. For example, for the output logic of XOR gate [0 1 1 0], if the output intensity of the 2-layer MLP system is [0.001, 0.013, 0.011, 0.002], we choose I 1 min and I 0 max as 0.011 and 0.002, respectively to calculate the visibility.
Since the coupling ratio of the directional couplers DC 1 , DC 2 , DC 3 and the phase delay of the phase modulators PM 1 , PM 2 , PM 3 are solved using Eqs. (2)- (14), the light intensity of the low level (logic 0) is null. The corresponding visibility of the output signals for all logic gates is unity.
During the fabrication of the directional couplers by optical fibers or by silicon waveguides, 1% error of the coupling ratio may happen. During the operation of the phase modulators by applying the voltage on the device, 1% error of the phase delay may occur. We calculate the visibility of the output signals as the coupling ratio of DC 1 , DC 2 , DC 3 and the phase delay of the phase modulators PM 1 , PM 2 , PM 3 are increased with 1% error. For  www.nature.com/scientificreports/ example, for XOR gate, α 1 obtained from Eq. (9) is 49% as listed in Table 2. As α 1 is increased from 49 to 50% (α A , α B , α C , α 2 , α 3 , ϕ 1 , ϕ 2 and ϕ 3 are left unchanged as listed in Tables 1 and 2), the visibility of the output signal is calculated to be 0.99. For another example, for the XOR gate, as ϕ 1 is increased from 8.88° to 12.48° (increasing 3.6° = 1% from -π to π), the visibility of the output signals is 0.91. For 100 calculations of different α A , α B , α C of each gates, the highest visibility of the 2-layer MLP system for all logic gates due to 1% error of the devices is listed in Table 3. We can observe that for 1% error of the coupling ratio of the directional couplers DC 1 , DC 2 and DC 3 , the worst visibility is 0.98. For 1% error of the phase delay of the phase modulators PM 1 , PM 2 and PM 3 , the worst visibility is 0.83. It seems that the results could be acceptable showing that the reconfigurable optical logic gates can be achieved even with the fabrication or operation errors. In electronics, a flip-flop or latch is a circuit that  www.nature.com/scientificreports/ can be used to store state information with a pair of cross-coupled NOR of NAND gates. The further application of the reconfigurable optical logic gates is to build the flip-flop. The optical memory could be realized.

Conclusion
In this work, we successfully establish an optical structure which can achieve EO logic gates. Thanks to this 2-layer-MLP structure, we can carry out the OR, AND, XOR, NAND, NOR and XNOR logic gates. In other words, we could take advantage of one optical neural network to achieve the most basic logic gates in optical approach. According to Eq. (5), we obtain the coupling ratio of the directional couplers DC 1 , DC 2 , and DC 3 and the phase delay of the phase modulators PM 1 , PM 2 , PM 3 under the ideal condition. The tolerance of the optical devices in our optical neural network is studied. The visibility changes of the output signals due to the 1% error during the fabrication and operation of the optical devices could be acceptable indicating that the reconfigurable optical logic gates can be realized in one optical configuration. Comparing our EO logic gates to the conventional electric logic gates, this EO logic gates have the capability of higher operating frequency, and high speed. In our study, the logic-gates functions among OR, AND, XOR, NAND, NOR and XNOR can be designed when the PMs and the coupling ratio of DCs are tuned in this EO logic gates. Thus, the control process is simpler. The present design uses the neural networks without recurrent property. The calculation performance could be faster than that of the previous work 5 . The optical logic gates can be applied to build an optical memory using the latch structure to store the information.

Data availability
The datasets used and/or analysed during the current study available from the corresponding author on reasonable request.